This invention relates to a refresh control circuit for a dynamic random access memory.
Dynamic random access memories (DRAM), which are widely used for data processing systems, store information with charges stored in their capacitance. Consequently, it is necessary to retrieve the stored information, amplify the signal level, and make recharge before discharge of the contents. This process is called "refreshing."
DRAM cells are arranged in rows and columns in the form of a matrix. All the memory cells in a row are refreshed by a single refreshing cycle. The refreshing operation requires a refresh timing signal and a refresh address signal which specifies the row to be refreshed.
A system including a processor equipped with a refresh address generator is shown in FIG. 3. This system includes a processor 10, a refresh frequency pulse generator 11, a refresh control circuit 12, a refresh address generator 13, an address bus 20, a data bus 21, a plurality of control signal lines 22, a DRAM control circuit 30, a memory timing control circuit 31, an address multiplexer 32, a memory address bus 33, and a DRAM 40.
The refresh address generator 13 is shown in more detail in FIG. 4. It includes a refresh address counter 14.
In operation, the processor 10 carries out arithmetic and logic operations and data rearrangement in memory locations of the DRAM 40 according to a program. The memory locations of the DRAM 40 are specified by the address signal on the address bus 20. The data to be transferred is transmitted in the direction specified by a signal on the control signal lines 22 at specified timing via the data bus 21. The upper portion of an address is used to determine the DRAM chip which has the desired memory location while the middle and lower portions are used to determine the row and column memory positions, respectively, in the DRAM. In general, it is necessary to output by time sharing row and column addresses on the memory address bus 33 to the DRAM 40. Consequently, the address multiplexer 32 outputs by time sharing the middle and lower portions of an address on the memory address bus 33 in synchronism with changes in the multiplex signal (MPX) from the memory timing control circuit 31.
On the other hand, the refresh frequency pulse generator 11 generates pulses at regular intervals informing the refresh control circuit 12 of the necessity of DRAM refreshing. At this point, it is necessary to provide the DRAM 40 with the row address of a memory to be refreshed. The position of a row address, which is the middle address portion on the address bus 20, varies with the type of a system depending on the memory capacity of a single DRAM. In order to make the refresh address generator 13 independent of the system, it is a common practice to not only output at the lower position of an address bus a refresh address indicative of the row position of a memory to be refreshed but also control the DRAM control circuit 30 via the control signal line 22 so that the address multiplexer 32 connects the lower address portion to the memory address bus 33 during a refreshing period. Thus, the row position of a memory to be refreshed is presented in the DRAM 40 for carrying out memory refreshing.
In order to minimize the time for the DRAM refreshing to use the bus, it is a common practice to simultaneously refresh all DRAM chips.
The address output from the refresh address generator 13, which is a value of the refresh address counter 14, is output on the address bus in response to a refresh address enable signal (RFADEN). The refresh address counter 14 is incremented by one for each refreshing cycle in response to a refresh address increment signal (RFADINC) so that when it repeats the refreshing process for the same times as the number of rows, all the memory cells of the DRAM 40 are refreshed.
Since the refresh address is output at the lower position of an address bus in the conventional refresh address generator, the following useless refreshing process is required for memory interleaving in the DRAM. Since data is read out of the DRAM a certain time after the previous one is read out, the memory interleaving has been developed to speed up the memory system.
As shown in FIG. 5, by the memory interleaving technique, addresses are divided into two banks; an odd number address bank and an even number address bank to place them on separate memory chips. That is, odd number addresses 1, 3, . . . are used for a DRAM 40a while even number addresses 2, 4, . . . are used for a DRAM 40b so that access to a continuous memory space becomes free of the above time constraint. In the 2-bank memory interleaving, the least significant bit of an address is used to designate the bank.
In order to reduce the number of refreshing cycles necessary for all the memory cells in such a DRAM 40, simultaneous selection of all the banks is made for performing refreshing. Consequently, the output of a refresh address at the least significant bit by the conventional refresh address circuit not only makes bank designation meaningless but also causes excessive refreshing, thus wasting the valuable system time.